Here are 73 public repositories matching this topic...

openhwgroup / cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

asic cpu fpga risc-v systemverilog-hdl rv64gc ariane

Updated Mar 16, 2026
Assembly

VUnit / vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

unit-testing asic fpga vhdl verification testbench verilog-hdl systemverilog-hdl universal-verification-methodology

Updated Mar 12, 2026
VHDL

nelsoncsc / ISP_UVM

A Framework for Design and Verification of Image Processing Applications using UVM

opencv image-processing hardware-designs systemc uvm systemverilog-hdl functional-verification

Updated Nov 27, 2017
SystemVerilog

SystemRDL / PeakRDL-regblock

Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.

asic fpga csr systemverilog registers systemverilog-hdl systemrdl systemrdl-compiler

Updated Dec 12, 2025
Python

pulp-platform / morty

A SystemVerilog source file pickler.

rust picklers rickandmorty systemverilog-hdl

Updated Oct 20, 2024
Rust

pulp-platform / axi_mem_if

Simple single-port AXI memory interface

asic fpga axi systemverilog-hdl

Updated Jun 7, 2024
SystemVerilog

nelsoncsc / easyUVM

A simple UVM example with DPI

uvm systemverilog-hdl functional-verification

Updated Aug 7, 2017
SystemVerilog

snbk001 / 100DaysofRTL

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore