Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.

Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.

Here are 2,454 public repositories matching this topic...

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mytechnotalent / Reverse-Engineering

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k2-fsa / sherpa-onnx

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platformio / platformio-core

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OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor

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A secure embedded operating system for microcontrollers

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alibaba / AliOS-Things

面向IoT领域的、高可伸缩的物联网操作系统，可去官网了解更多信息https://www.aliyun.com/product/aliosthings

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chyyuu / os_kernel_lab

OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32

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misprit7 / computerraria

A fully compliant RISC-V computer made inside the game Terraria

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mortbopet / Ripes

A graphical processor simulator and assembly editor for the RISC-V ISA

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Updated Feb 18, 2026
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Limine-Bootloader / Limine

Modern, advanced, portable, multiprotocol bootloader and boot manager. (Official mirror of https://codeberg.org/Limine/Limine)

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openhwgroup / cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.