ghdl - 技术专题深度解读 | GitHub 中文社区

ghdl / ghdl

VHDL 2008/93/87 simulator

simulator compiler hardware llvm vhdl gcc ghdl hacktoberfest testbench

Updated Jul 23, 2026
VHDL

olofk / edalize

An abstraction library for interfacing EDA tools

fpga simulation vhdl eda verilog xilinx synthesis vivado altera systemverilog icestorm lattice icarus-verilog modelsim ghdl yosys verilator riviera-pro fossi spyglass

Updated Jul 2, 2026
Python

suoto / hdl_checker

Repurposing existing HDL tools to help writing better code

python vim language-server vhdl verilog xilinx syntax-checker systemverilog hdl modelsim questasim ghdl xilinx-vivado lsp-server coc-nvim vim-ale vivado-simulator mentor-msim hdl-checker emacs-lsp

Updated Jun 21, 2026
Python

jakubcabal / spi-fpga

Sponsor

SPI master and SPI slave for FPGA written in VHDL

fpga controller vhdl accelerometer spi ghdl spi-master spi-slave cyc1000 spi-loopback spi-controller

Updated Apr 24, 2021
VHDL

PyFPGA / pyfpga

A Python package to use FPGA development tools programmatically.

python fpga diamond tcl trellis vivado ise icestorm ghdl yosys quartus nextpnr libero

Updated Mar 22, 2025
Python

wyvernSemi / pcievhost

PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

c verification verilog virtual vivado modelling icarus-verilog ghdl cosim pcie pli bfm verilator nvc xsim questa-sim

Updated Jun 16, 2026
C

jakubcabal / uart-for-fpga

Sponsor

Simple UART controller for FPGA written in VHDL

fpga simulation controller vhdl uart ghdl wishbone uart-controller wishbone-bus cyc1000 uart-loopback

Updated Aug 7, 2021
VHDL

openlab-x / OpenCircuitX

Free, open-source EDA platform for VHDL and Verilog. HDL editor, circuit canvas, RTL viewer, waveform viewer, and FPGA toolchain in one window.

open-source fpga cpp vhdl ide wxwidgets eda circuit-simulator rtl verilog digital-logic systemverilog hdl ghdl yosys hardware-design waveform-viewer

Updated Jul 20, 2026
C++

stnolting / neorv32-verilog

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

asic fpga verilog icarus-verilog ghdl neorv32

Updated Dec 3, 2025
VHDL

stnolting / neorv32-setups

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

fpga vhdl intel verilog xilinx lattice soc ghdl yosys risc-v neorv32

Updated Jul 27, 2026
VHDL

VHDL / PoC

IP Core Library - Published and maintained by the Open Source VHDL Group

library asic collection fpga vhdl diamond verification xilinx synthesis vivado altera hdl ghdl quartus nvc ipcore

Updated Jul 14, 2026
VHDL

Paebbels / JSON-for-VHDL

A JSON library implemented in VHDL.

parser json fpga simulation vhdl xilinx synthesis lattice fileformat modelsim questasim ghdl

Updated Jul 13, 2026
VHDL

tmeissner / psl_with_ghdl

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

vhdl assertions ghdl formal-verification yosys psl symbiyosys functional-coverage

Updated Feb 16, 2026
VHDL

mnemocron / my-discrete-fpga

My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.

fpga vhdl ghdl fpga-soc 7400 breadboard-computer

Updated Apr 20, 2024
VHDL

Stokpan / E80

Educational VHDL computer with a single-click toolchain for assembly, simulation, and execution on FPGAs

cpu max7219 assembly vhdl isa microworld modelsim ghdl yosys quartus gowin gatemate tang-primer-25k

Updated Jul 6, 2026
VHDL

ghdl / docker

Scripts to build and use docker images including GHDL

dockerfiles hardware ci simulation vhdl actions verilog synthesis icestorm gtkwave ghdl testbench vunit yosys openocd pnr nextpnr prjtrellis

Updated Nov 20, 2024
Shell

tmeissner / formal_hw_verification

Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog systemverilog ghdl formal-verification yosys psl symbiyosys

Updated Mar 7, 2024
VHDL

tmeissner / cryptocores

cryptography ip-cores in vhdl / verilog

cryptography fpga vhdl verilog testbenches ghdl

Updated Feb 20, 2021
VHDL

dbhi / vboard

Virtual development board for HDL design

vhdl verilog hdl ghdl cosim vpi verilator fli vhpidirect

Updated Mar 31, 2023
VHDL

stnolting / neorv32-riscof

✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.

processor vhdl verification riscv isa ghdl risc-v neorv32 riscof sail-riscv

Updated Feb 22, 2026
Python

ghdl - 技术专题

Here are 120 public repositories matching this topic...