asic - 技术专题
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OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds
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Mar 25, 2026 - Python
RISC-V CPU Core (RV32IM)
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Sep 18, 2021 - Verilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Jul 23, 2026 - SystemVerilog
Haskell to VHDL/Verilog/SystemVerilog compiler
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Jul 25, 2026 - Haskell
32-bit Superscalar RISC-V CPU
linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors
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Sep 18, 2021 - Verilog
RISC-V XV6/Linux SoC, marchID: 0x2b, 0x34
linux asic cpu fpga x11 riscv verilog xv6 systemverilog mmu soc system-on-chip rv32ima chipdesign tinytapeout sv32
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May 29, 2026 - Verilog
Digital Signature Service : creation, extension and validation of advanced electronic signatures
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Jul 24, 2026 - Java
VUnit is a unit testing framework for VHDL/SystemVerilog
unit-testing asic fpga vhdl verification testbench verilog-hdl systemverilog-hdl universal-verification-methodology
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May 14, 2026 - VHDL
The PoC Library has been forked to github.com/VHDL/PoC. See new address below
python asic fpga simulation vhdl verification xilinx synthesis regression-testing altera hardware-designs lattice hardware-libraries poc-library vlsi testbenches hardware-modules osvvm uvvm vunit
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Jul 30, 2025 - VHDL
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
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Feb 3, 2024