Here are 530 public repositories matching this topic...

google / skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

magic asic eda pdk asic-library openroad openram skywater

Updated Oct 28, 2024
Python

openhwgroup / cva6

The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.

asic cpu fpga risc-v systemverilog-hdl rv64gc ariane

Updated Mar 16, 2026
Assembly

stnolting / neorv32

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

microcontroller asic cpu fpga processor vhdl verilog soc risc-v soft-core

Updated Mar 17, 2026
VHDL

olofk / serv

SERV - The SErial RISC-V CPU

asic fpga verilog risc-v

Updated Feb 19, 2026
Verilog

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Sep 15, 2025
Python

ultraembedded / riscv

Sponsor

RISC-V CPU Core (RV32IM)

asic cpu fpga verification verilog pipeline-processor risc-v rv32i verilator riscv-linux rv32im

Updated Sep 18, 2021
Verilog

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

haskell asic fpga vhdl verilog systemverilog hardware-description-language

Updated Mar 15, 2026
Haskell

pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

asic fpga hardware rtl ip systemverilog axi network-on-chip axi4 axi4-lite

Updated Mar 11, 2026
SystemVerilog

ucb-bar / gemmini

Berkeley's Spatial Array Generator

asic accelerator dnn

Updated Mar 17, 2026
Scala

ultraembedded / biriscv

Sponsor

32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar in-order risc-v branch-prediction coremark rv32i verilator riscv-linux rv32im artix-7 pipelined-processors

Updated Sep 18, 2021
Verilog

siliconcompiler / siliconcompiler

Modular hardware build system

asic fpga hls vhdl eda rtl verilog make synthesis cmos

Updated Mar 17, 2026
Python

splinedrive / kianRiscV

RISC-V XV6/Linux SoC, marchID: 0x2b

linux asic cpu fpga x11 riscv verilog xv6 systemverilog mmu soc system-on-chip rv32ima chipdesign tinytapeout sv32

Updated Mar 3, 2026
Verilog

esig / dss

Digital Signature Service : creation, extension and validation of advanced electronic signatures

java asic validation signature xades cades pades esignature jades

Updated Mar 6, 2026
Java

riscvarchive / riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

asic fpga risc-v socs open-isa

Updated Mar 26, 2021

ultraembedded / cores

Sponsor

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi sram uart verilog-hdl verilog-components verilator i2s sdram

Updated Jul 1, 2021
Verilog

VUnit / vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

unit-testing asic fpga vhdl verification testbench verilog-hdl systemverilog-hdl universal-verification-methodology

Updated Mar 12, 2026
VHDL

VLSI-EDA / PoC

The PoC Library has been forked to github.com/VHDL/PoC. See new address below

Updated Jul 30, 2025
VHDL

zssloth / Embedded-Neural-Network

collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning

compression asic fpga deep-learning neural-network

Updated Feb 3, 2024

pulp-platform / ara

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core

asic cpu vector riscv ara rvv rv64gcv

Updated Mar 16, 2026
C

google / gf180mcu-pdk

PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

asic eda pdk openroad 180nm globalfoundries gf180mcu

Updated May 31, 2023
Makefile