SAR ADC design knowledge base for agentic IC design: architecture, CDAC, comparator, bootstrap, async logic, integration, and Spectre verification. Includes taped-out 11-bit reference.
- Updated
Apr 5, 2026
SAR ADC design knowledge base for agentic IC design: architecture, CDAC, comparator, bootstrap, async logic, integration, and Spectre verification. Includes taped-out 11-bit reference.
Complete 2.4 GHz RF receiver front-end designed in Cadence Virtuoso (180 nm CMOS) — cascode LNA, Gilbert cell mixer, and Gm-C IF filter. Serving as the analog verification layer for a 64 subcarrier OFDM PHY baseband. Simulated in Spectre RF.
This project implements a tetrahedral oscillator inspired by the paper “Analysis and Design of a Tetrahedral Oscillator” by Richelle L. Smith and Thomas H. Lee. The oscillator is built from coupled inverter pairs, and its operating frequency is tuned by adding capacitive loads to the internal nodes.
Analog circuit reasoning gate before paper-circuit replication, sizing, and simulation.
Ngspice DIAMOND testbench template (SCH+PEX) for IHP SG13G2 with DC/TRAN/AC + CSV summary
Minimal inkjet printhead driver IC exploration using the GF180MCU open PDK, focusing on high-voltage device layout and mixed-signal integration.
CAN FD / CAN SIC 中文知识库:面向模拟 IC 设计工程师与嵌入式工程师,覆盖协议、位定时、物理层、收发器设计、测试认证与资源索引,含收发器模块参数设计要点。