RISC-V soft core running on Colorlight 5B-74B.
Risc-V Cores
The market for processors and microcontrollers is increasingly heated, and with the launch of the ISA (Instruction Set Achitecture) RISC-V, an open specification, it opens up a new opportunity for …
basic example of litex on colorLight 5A-75B based on fpga_101/lab004
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Rocket Chip Generator
Source files for SiFive's Freedom platforms
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of booting Linux.
RiscyOO: RISC-V Out-of-Order Processor
Cornell CSL's Modular RISC-V RV64IM Out-of-Order Processor Built with PyMTL
A 32-bit RISC-V soft processor
A 32-bit Microcontroller featuring a RISC-V core
A FPGA friendly 32 bit RISC-V CPU implementation
RISC-V CPU Core
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.
PicoRV32 - A Size-Optimized RISC-V CPU
MR1 formally verified RISC-V CPU
SERV - The SErial RISC-V CPU